The present invention relates to a frequency synthesizer which is dynamically programmable to generate a synthesized frequency signal, and more particularly, to such a frequency synthesizer including at least one phase lock loop operative in a selected loop bandwidth state and including a dynamically programmable control circuit for setting the frequency range of its selected loop bandwidth state.
A frequency synthesizer generally includes at least one phase lock loop comprising the elements of a phase detector, charging circuit, a storage device including a capacitive element, a voltage controlled oscillator, and a frequency divider network. In operation, the phase detector is governed by a very stable reference frequency signal and a feedback frequency signal to generate at least one control signal which governs the charging circuit to source or sink current to and from a capacitive element at a current level (loop bandwidth) to adjust the voltage across the capacitive element of the storage device. The voltage controlled oscillator generates a synthesized frequency signal proportional in frequency to the adjusted voltage. The frequency divider network divides the synthesized frequency down to the feedback frequency signal.
In a programmable frequency synthesizer, the frequency of the synthesized frequency signal is dynamically set by programming the frequency divider network with a coded digital word. Accordingly, a phase lock loop of the frequency synthesizer may be randomly switched between an old and new synthesized frequency signal by programming a different digitally coded word into the frequency divider network.
Each time the phase lock loop is dynamically set to generate a new synthesized frequency signal, the feedback frequency signal is caused to deviate in phase and frequency from the reference frequency signal initially and then relocked thereto within a time interval dictated by the loop bandwidth setting of the phase lock loop. In most phase lock loops, the loop bandwidth is established by setting the current level which the charging circuit uses to adjust the voltage across the capacitive element of the storage device. Most contemporary frequency synthesizers operate with two loop bandwidths or commensurate current level settings. A low loop bandwidth or current level setting is generally established to maintain lock of the synthesized frequency signal to a current synthesized frequency setting. This low setting offers filtering and stability to reduce substantially synthesized frequency jittering as a result of electrical noise either self-induced or otherwise.
In addition, for those applications in which the frequency synthesizer is used in a battery operated portable electronic device, the low current level setting produces little drain on the battery, thus allowing for a longer battery life. However, the low current level setting is not considered adequate for relocking the current synthesized frequency signal to a new frequency setting because, in most applications, the relock time is required to be held to a minimum. Thus, for these purposes, a second wider loop bandwidth setting may be selected in accordance with the relocking operational state of the phase lock loop.
Examples of contemporary phase lock loops having dual loop bandwidth settings are shown and described in the following U.S. Patents:
(1) U.S. Pat. No. 4,167,711 entitled "Phase Detector Output Stage for Phase Locked Loop" issued to George Smoot on Sept. 11, 1979, and PA1 (2) U.S. Pat. No. 4,771,249 entitled "Phase Locked Loop Having a Filter with Controlled Variable Bandwidth" issued to Burch et al. on Sept. 13, 1988,
both patents being assigned to the same assignee as the instant application.
While the foregoing described frequency synthesizer with low and high (wide) loop bandwidth settings is adequate for many applications, there may be need for improvement for more recently defined applications. New and greater performance requirements are being imposed for certain applications of frequency synthesizers. For example, in a battery operated electronic device, it is proposed that a frequency synthesizer be capable of randomly selecting between synthesized frequency settings over a very wide scan frequency range, say on the order of a few megahertz, for example, and relocking within a short time duration. Under these specifications, it is recognized that there are conflicting needs. For example, to ensure that the specified relock time is always met, a very high current level may be set for the relocking bandwidth state to meet the worst case condition which is when the synthesized frequency setting is switched from one end of the span frequency range to the other. However, that means that a higher than necessary current level will be used for all other frequency switching conditions creating a higher drain on the battery source of the electronic device for most cases. In addition, because of the wide scan frequency range, an adequate low bandwidth setting for stabilization when operating at one end of the span frequency spectrum may result in an undesirably higher than necessary drain on the battery source when operating at the other end thereof.
It appears that in order to meet the higher performance specifications of the foregoing described type of application, it is of paramount importance to provide a frequency synthesizer capable of being dynamically programmed to vary the frequency range or current level of the selected loop bandwidth state of a phase lock loop thereof. With this capability, each time the frequency synthesizer is programmed with a new synthesized frequency setting, it may also be dynamically programmed with an optimum frequency range for the selected loop bandwidth state in accordance with the new synthesized frequency setting. In so doing, an adequate loop bandwidth setting is assured to meet the rigid specifications of the application while minimizing the current drain on the battery source.